1. Field of the Invention
The invention relates to short-channel transistor devices, and particularly transistors having a channel length less than 0.25 .mu.m.
2. Description of the Related Art
With the continuing quest to define and produce transistors having ever-smaller overall cell geometries that are capable of operating at increasing switching speeds, many variations on the conventional self aligned channel region have been attempted. For the purposes of this application, cell geometry is defined as the two-dimensional surface area required for implementing a single, integral active lodging element, typically an -- or P-channel resistor or a pair of complementary transistors. Cell geometry can be distinguished from transistor geometry in that the latter refers to the three-dimensional structure of a single integral logic element.
Typically, MOSFET transistors are manufactured in a symmetrical fashion. That is, the semiconductor substrate has a gate stack formed thereon, whether the gate stack is a single polysilicon gate, or a floating gate design, and source or drain regions are thereafter implanted with a gate stack in place so that the source and drain regions are "self-aligned" to the gate stack. Variations of this technique include the lightly-doped drain (LDD) transistor wherein spacers are formed about the gate stack and lightly-doped regions are formed below the spacers and adjacent to the more heavily-doped source and drain regions in order to avoid device punch-through and other short-channel effects which are seen in transistor devices as the channel length of the devices approaches 0.35 .mu.m or less.
As the miniaturization of MOSFETs continues, scaling of devices below the 0.25 .mu.m regime, and in particular, below the 0.15 .mu.m regime presents an entirely new set of challenges to the transistor designer.
One particular solution which has been explored with respect to sub-0.15 .mu.m devices is the asymmetric channel device. In general, the asymmetric channel device is formed by using an angled implant of an impurity on the source side of the device while masking the drain side so that a portion of the implant underlies the gate stack forming a more lightly-doped region than the adjacent drain region.
In the quarter-micron regime, asymmetric n-channel MOSFET devices have been proposed to achieve high current drive-ability and hot-carrier reliability. In a paper by Odanaka , et al., entitled "Potential Design and Transport Property of 0.1-.mu.m MOSFET with Asymmetric Channel Profile," IEEE Transactions on Electron Devices, Vol. 44, No. 4 (Apr. 1997), the authors describe the exploration of the relationship between device performance and transport property of a 0.1 .mu.m n-channel MOSFET with an asymmetric channel profile through Monte Carlo device simulations and measured electrical characteristics.
The experimental device taught therein has a gate oxide thickness of 4 nanometers and a polysilicon gate height of 200 nanometers. Processing of the device is equivalent to that of a conventional symmetrical device, except that the V.sub.t channel implant, which is utilized to adjust the threshold voltage of the device, is performed by a threshold adjustment implantation with an orientation non-normal to the surface of the substrate after gate electrode formation. For such a channel implant, an 80 KeV BF.sub.2 ion dose of 1.times.10.sup.13 cm-2 is implanted with a tilt angle of 7.degree.. Of note is that this implant is on the source side only of the devices, and no masking of the device during the V.sub.t implant is discussed. The reference teaches that the asymmetry of the lateral channel profile becomes weak as the BF.sub.2 energy decreases. After gate electrode formation, arsenic ions with a dose of 1.times.10.sup.14 cm-2 were implanted at an energy of 10 KeV to form shallow source/drain extensions. Subsequently, deep source/drain regions are formed with a high arsenic dose of 6.times.10.sup.15 cm-2 at an energy of 40 KeV, followed by a rapid thermal anneal at 1,050.degree. C. for ten seconds.
In a symmetrical short channel MOSFET, a number of implants are used to control the V.sub.t threshold voltage. In particular, a substrate will typically have formed thereon an epitaxial silicon layer overlying the bulk silicon layer of the semiconductor substrate.
A shallow implant of, for example, a P-type impurity such as boron or BF.sub.2 will be implanted into the channel region wherein the device is to be formed. The energy of the implant will be in a range of about 10-30 KeV to a junction depth of about 100 .mu.m.
Subsequently, a punch-through stop implant at an energy of about 40-100 KeV to a junction depth of about 0.25 .mu.m will be made into the epitaxial silicon. This pushes dopants further down into the substrate and increases the resistance of the channel.
Finally, a third, approximately 200 KeV implant may be used in addition to form a deep punch-through stop implant at a depth of about 0.5 .mu.m.
While the teachings of the Odanaka reference obviate the need for such multiple implants, little control over the implant process and the design and distribution of the implant concentration is disclosed.